Christopher Bengel received the B. He is currently pursuing the Ph. Leon Dixius was born in Trier, Germany, in He received his B. He received the Gottfried Wilhelm Leibniz Preis in Dirk J. He received the Diploma degree and the Ph. Computation-in-Memory accelerators based on resistive switching devices represent a promising approach to realize future information processing systems.
These architectures promise orders of magnitudes lower energy consumption for certain tasks, while also achieving higher throughputs than other special purpose hardware such as GPUs, due to their analog computation nature. Due to device variability issues, however, a single resistive switching cell usually does not achieve the resolution required for the considered applications. To overcome this challenge, many of the proposed architectures use an approach called bit slicing, where generally multiple low-resolution components are combined to realize higher resolution blocks.
In this paper, we will present an analog accelerator architecture on the circuit level, which can be used to perform Vector-Matrix-Multiplications or Matrix-Matrix-Multiplications.
The components are designed to handle the variability of the resistive switching cells, which is verified through our verified and physical compact model. We then use this architecture to compare different bit slicing approaches and discuss their tradeoffs.
The dominance and commercial success of machine learning algorithms for the processing of images, speech and video signals [ 1 ] in the last ten years, has largely been enabled by the utilization of Graphics Processing Units GPUs during training [ 1 , 2 ]. These successes have further lead to the development of Application Specific Integrated Circuits ASICs , specifically targeted for machine learning workloads.
